A typical disk includes a series of tracks or channels which are concentrically arranged. These tracks are written and read by a head which senses the information stored on the disks. This information may include format information, as well as, user information. When this information is read by the head it is transferred to various circuits for interpretation. This circuitry may be known as a read channel circuit.
In attempting to design read channel devices to read, for example, hard disk drives, many designs have been presented in order to achieve high area density on the hard disk drive while maintaining the synchronization necessary to read every data area located on the hard disk drive.
FIG. 1 illustrates typical information loaded onto a hard disk drive in order to achieve the proper synchronization with each of the data areas. The information required for such synchronization includes a preamble 100 necessary to achieve the synchronization.
The ID field 102 is used to identify the particular data sector while the digital acquisition field may be used to acquire the correct phase. However, the use of such a format introduces a significant overhead in the actual data stored.
The data stored and used by the user will be significantly reduced by the digital acquisition phase synchronization preamble required for the read operation. Thus, if these fields could be made smaller or eliminated entirely the data field containing the actual user data could be increased.
One solution to this problem has been the use of partial response maximum likelihood (PRML) to achieve high area density on hard disk drives. Typically, a PRML channel gains about 30-40 percent more storage capacity than a conventional peak-detection channel.
FIG. 2 illustrates a typical hard disk drive system including the analog front end signal processor and a companion digital ASIC. The analog read signal goes through an automatic gain control (AGC) and filter path and the filter is synchronously sampled by the A/D converter (ADC) which is clocked by the synchronizer SNC phase lock loop PLL. The digitized samples are input to the digital chip where it is further processed by a finite-impulse-response FIR digital filter which equalizes the signal to a PR4 partial response spectrum shape. The signal is finally passed through a Viterbi detector which performs a maximum likelihood sequence detection. The digital read data is then output.